CCD Process

Teledyne DALSA Semiconductor's 150mm C25 2.5µm CCD process offers buried channel or surface channel operation at up to 15 volts with either two or three polysilicon layers. A modular processing approach allows our foundry customers to adjust process parameters for the most demanding requirements on CTE, charge storage capacity and low dark current. Scanner photolithography permits integration of wafer scale devices. We offer advanced technology such as stitching for large devices and more.

Teledyne DALSA is proud that our base process is fully tunable. Customers specify the buried channel and barrier implants that suit the application. Channel stops, anti-blooming implants, or other special features can be added. Successful projects have included PMOS CCDs for radiation hardness, the world's higest resolution monolithic device (10.5k x 10.5k, 111 megapixels), and high-resistivity devices.

Typical applications for these products are in scientific, industrial, or even space deployments. Custom variants of this process supply many of the image sensors used in the industry-leading digital cameras of Teledyne DALSA's Machine Vision division. NASA's JPL chose Teledyne DALSA to fabricate the image sensors on the Mars Rovers, which captured the highest-resolution images ever taken of another planet.

To support all our customers' custom CCD processes, we offer a wide range of services from mask manufacturing to complete device characterization.

Teledyne DALSA Semiconductor operates its CCD Wafer Foundry Service as an independent arm from any of the other Teledyne DALSA group of Business Units. Customer information and data confidentialty is assured.

Process Capability Parameters

C25 CCD Process Spec
Datasheet	C25 Datasheet
Wafer Size	150 mm (Max. die 10x10 cm)
Poly Layers	2 or 3
Poly Overlaps	0.5 µm
Metal	Single / Double / Triple
Projection Aligner	2.5 µm 1X (MPA-600)
Maximum Operating Voltage	15 V
Charge Transfer Efficiency (CTE)	> 99.999%
Dark Current	Low (< 1nA/cm2 )
Other	PCM Electrical Wafer Acceptance Wafer Probe Testing Surface and Buried Channel Operation Customizable Process Customized Starting Material Short cycle time
Special Options	Mix & Stitch of multiple stepper fields PMOS CCD for rad-hard High Resistivity CCDs (100 Ω-cm to 10 kΩ-cm ) Patent pending Ti/TiN metalisation for high T° post-processing

Support Data

• Design Rules: CCD 2.5, 3.0 µm NMOS Buried-Channel Double/Triple-Poly, Double/Triple Metal Process. New updated design rules available, with significantly expanded details and capabilities. Contact Teledyne DALSA Semiconductor to receive the expanded document.

Legacy CMOS Processes

Teledyne DALSA Semiconductor has maintained manufacturing capability for many legacy processes. Our expertise in flexible manufacturing ensures clients are able to maintain a technology path with older technologies for many years, especially for difficult analog and mixed-signal designs.

We can transfer your existing designs onto Teledyne DALSA Semiconductor CMOS, making the process modifications necessary to replicate the performance of these products. Our design rules are carefully defined to ease portability.

Process	C08C	C12C	C15 A/B/C	C20 B/C	C30 B/C/D	C40C
Datasheet	C08C	C12C	C15	C20	C30	C40C
Geometry	0.8µm	1.2µm	1.5µm	2µm	3µm	4µm
Voltage	3-5	5	1.2,3,5	3,5	5,10	5-10
Poly Layers	1-2	1-2	1-2	1-2	1-2	1-2
Metal Layers	1-3	1-3	1-3	1-2	1-2	1-2
Wafer Size	6"	6"	6"	6"	6"	6"

Implantation

Ion implantation is the standard method for the doping of silicon in CMOS/CCD technologies. We offer the following capabilities:

• in the 1E11-1E14 at/cm² range, implantation of boron, phosphorus and arsenic in the 5-500 keV range
• in the 1E14-1E17 at/cm² range, implantation of boron, phosphorus and arsenic in the 5-200 keV range

Other capabilities can be developed upon request.